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[VHDL-FPGA-Verilog] pwm

Description:
Platform: | Size: 214016 | Author: 熊辉波 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: PLL 时钟模块　　Quartus II平台的简单设计实例　附仿真波形-PLL clock module Quartus II platform attached to a simple design example simulation waveforms
Platform: | Size: 806912 | Author: 许东滨 | Hits:

[VHDL-FPGA-Verilog] SPWM_ADC_LCD

Description:
Platform: | Size: 125952 | Author: zyb | Hits:

[VHDL-FPGA-Verilog] SPWM

Description: VHDL采用自然采样法写的SPWM，里面有正弦表，可以通过外接输入正弦波和三角波的频率。 -VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
Platform: | Size: 7168 | Author: zyb | Hits:

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